The present invention relates to a DRAM stacked packages, a DIMM, a method for testing them, and a semiconductor manufacturing method.
One of the conventional test methods for testing semiconductor devices is known from Japanese Patent Laid-open No. 2001-35188 (patent document 1). The patent document 1 discloses a method for testing a semiconductor device in which at least three on-chip DRAMs are mounted and each can be independently accessed and at least one of the three DRAMs is different in storage capacity from the other DRAMs. When each of the DRAMs is tested by inputting an independent test address signal into each DRAM, with a DRAM whose test time is the longest being excluded, the other DRAMs (at least two) are serially tested, and in parallel with this serial test, the DRAM whose test time is the longest is tested.